Monarch Technologies Group is a North American distributor of high-end EDA software for the semiconductor chip-design community. These newsletters are an on-going discussion of emerging EDA technologies, applications, design issues, and business topics.

In This Issue:

March 3, 2005  -  Volume 3, Issue 2

  • Commentary:  The Academy Awards... EDA Version

  • Cool Application (5): Analyze & View SystemVerilog Assertions

  • Cool Application (6): Diagnostic/Prognostic IP Library improves MTBF by 5X!

  • The Monarch eVC Shop: Cadence CEO's Letter to Verisity Customers

  • What's New: $1M order, Free Browser Update, Mar/Apr Forums & Seminars

  • Monarch's EDA Portfolio:  Data Sheets & White Papers & Down-loads

 

The Academy Awards...

EDA Version

 

by Bill Hoolhorst

 

 

On the first three days of February, in Santa Clara, California, DesignCon 2005 featured three keynote speakers on three consecutive days. Monday: Mike Fister, President & CEO, Cadence Design Systems; Tuesday: Dr. Aart de Geus, Chairman & CEO, Synopsys: and, Wednesday: Dr. Wally Rhines, Chairman & CEO, Mentor Graphics. Since these three players represent over 80% of the entire EDA Market, there was great anticipation by attendees to be able to hear from each competitor.

 

Us humans are a competitive bunch, so if human nature prevails, the first question that will be asked after the last keynote ends will be "WHO WON ?". Since CEOs are basically actors at heart (part of the job description, I think), maybe they should be measured like actors are measured! Thus, for their DesignCon 2005 performances, here are Monarch's results of the competition for the ultimate ego prize, the Academy Awards (of EDA).

 

THE NOMINEES FOR BEST PERFORMANCE:

 

Mike Fister - CEO, Cadence Design Systems

Mike is this years Rookie. This dark horse brings a fresh view to the competition. We have seen very few on-screen performances from Mike, making this mystery man the key attraction. Off-screen, his controversial statements regarding the down-sizing of Cadence's participation at DAC, and his acquisition of Verisity's "e" language makes this keynote performance a "must see".

 

Dr. Aart de Geus - Chairman, CEO, Synopsys

A brilliant, seasoned actor, known mostly for his roles as technical guru. Often type-cast as technology evangelist, secretly promoting product hype as esoteric technology. Aart's weakness has been in the scripts he has accepted, which usually have come across as too transparent. His script writers fail to camouflage blatant, thinly disguised product infomercials without audience detection.

 

Dr. Wally Rhines - Chairman, CEO, Mentor Graphics

Another brilliant, seasoned performer, who, like de Geus, has suffered from scripts without much meat. Often criticized for playing roles that lack story line. Past narratives have failed to provide a reasonable story FLOW... a beginning (front-end) and a back-end, but no middle. Like in the tortoise and the hare, Wally has developed a style using a tortoise strategy for slow but continuous growth.

 

As with most awards at this level, all of the nominees are the cream of the crop, the best of the best. Since we are judging on a single individual performance, the outcome will depend on many things. Like a final exam, this one performance is a significant portion of the grade. And, at this level of play, on any given day the winner could be anyone.

 

AND THE ENVELOPE, PLEASE...

 

The brass ring at this event is, of course, BEST PICTURE... however, all of the nominees did receive some "BEST OF... " award. Like trying to compare Marlin Brando to Shirley Temple, each has his own strengths and weaknesses in various categories. With this strong field, each grabbed a category, but only one got the Brass Ring.

 

Monday, Feb. 1 - Performance by Mike Fister, Cadence:

 

OOPs... The auditorium of the Santa Clara Convention Center was packed. The audience was anxious to hear what Mike was going to say. Ted Vucurevich, Cadence's Chief Technology Officer, stepped to the podium and announced that this day he would be representing Cadence and would be giving the keynote address. Fister was a no-show!!! You could hear the groans from the audience. Reason??? Ted explained that Mike had an "urgent" meeting he had to attend in Israel regarding the Verisity acquisition. A really bad first impression for Mike. It sounded something like "the dog ate my homework". Hopefully, this is not foreshadowing of a new "business style"... attitude? [Editors Note: Mike did show up at the EDA Consortium's "CEO Forecast and Industry Vision" event on Feb. 24th.... so maybe this was just a one-off situation] Of course, this eliminated Fister from the competition.

 

Under the circumstances, though, Ted pulled off a difficult substitution. He handled it like a trooper. No excuses, no whining, no half-hearted jokes. His presentation was a somewhat canned technical rah-rah piece that may not have been the best match for this Silicon Valley audience, but with no warning, it was acceptable. And, for his valiant effort as a pitch hitter, we give the BEST SUPPORTING ACTOR award to Ted Vucurevich.

 

 

Tuesday, Feb. 2 - Performance by Aart de Geus, Synopsys:

 

Aart gave a really brilliant performance. The script writing in this role was much improved, and he raised his personal best to a new level. The theme was "Think Systemic" where Aart compared the high tech world with the field of economics, and his experience with humanitarian issues he was currently involved with. Aart's message was that you have to look at the whole system to really solve the individual issues that make up the whole. For example, to solve the poverty issue in 3rd world countries, you must also consider education, health and corruption. de Geus magically segued into the EDA world by implying that to solve deep issues like design at 45nm, you must look at all of the system issues. Aart listed a dozen other things that had to be optimized, compromised and traded off.

 

As the drama continued we learn that all of these issues have tools associated with them, and to make trade-offs they better be able to talk to one another, and all of these tools better be able to work together in a FLOW. This was definitely not a product pitch as in the past, but, like some of those movies that end without an ending (you know, you have to fill in the blanks) there was this mild panic... Oh My God, where am I going to get all of these integrated tools? I guess probably from Synopsys (or maybe Cadence??). In fairness, maybe I'm overdoing this transparency thing, looking for a flaw in a flawless performance. With that said, we give the BEST ACTOR IN A DRAMA award to Aart de Geus.

 

 

Wednesday, Feb. 3 - Performance by Wally Rhines, Mentor Graphics:

 

On the last day of competition, Wally Rhines gave a truly ground breaking performance. Wally took a risk and through out some thoughts and ideas for consideration that were truly visionary. Unlike typical keynoters who's crystal ball forecasts are based on Data Quest numbers, or their quarterly analysts conference call projections, Rhines went out on a limb and surmised that in 10 years the number of chip designers could increase an order-of-magnitude to 5,000,000....  5,000,000!!! WHERE DID THAT COME FROM?

 

Well, here is how Dr. Rhines came to this conclusion: Much interesting (and disturbing) backup data was first presented... 2 year trend per geometry generation moving to 3 years, 180nm is still 80% of mainstream, number of design starts going down (and if linearly extrapolated, will reach zero by 2011 - chuckle from audience), 10 year Makimoto wave of Customization to Standardization, 15 year level-of-abstraction cycle.

 

And, then, Wally focused on the level-of-abstraction cycle. Abstraction levels have evolved from TRANSISTORS to GATES to RTL and the next leap will probably be to PLATFORM-BASED-DESIGN.

  • In the 1960s there were 5,000 Custom Designers.

  • In the 1980s there were 50,000 ASIC Designers.

  • In 2005 there are 500,000 FPGA Designers.

  • So, how about in 2015 there could be 5,000,000 Platform Based Designers?

"Abstraction enables more people of other disciplines to participate".... system level garage inventors... AMATEUR INNOVATORS! But, even Rhines admitted that this is purely speculation and that linear extrapolations are often dangerous (remember the design starts going to zero in 6 years). However, maybe he's not so far off. If someone had told me 10 years ago that in the next decade there would be a market in which an average consumer could use general purpose PC software to remove red-eye and do professional touchup on their photo snap-shots, I would have thought they were nuts. Therefore, for his vision, we give the brass ring of the Academy Awards, the BEST (BIG) PICTURE to Wally Rhines.

 

For a really in-depth review of DesignCon 2005, see Peggy Aycinena's  One point of view out of many ...

And, Jack Horgan's DesignCon 2005 from EDA Weekly.

 

Comments welcome at BillH@MonarchTechGroup.com

 

 

Cool  Application (5)

 

 

Analyze & View SystemVerilog Assertions

 

In an attempt to increase the success rate of new ASIC designs, many companies have been building in PSL and SystemVerilog assertions to their designs in order to do a more thorough job of verification. Today's designs can easily have over 20,000 lines of assertion code in the larger ASIC designs. It is expected that the next generation of designs will have over 100,000 lines of assertion code. With increasing numbers of lines of assertion code, it is difficult to even verify that the assertions are actually testing exactly what the design engineers had intended these assertions to test.

 

NOW THERE IS AN ANSWER

The popular Veritools Undertow™ source code debugger and waveform viewer are used in over 1000 companies. And, now Veritools has added ASSERTION ANALYSIS to their feature set.

 

HOW DOES IT WORK?

Veritools integrates assertion support into Undertow Suite in two ways: 1) analysis of simulation results from simulators that can support assertions as part of their input language, and 2) analysis directly from any waveform file generated from Verilog/VHDL or SystemVerilog by using a new tool that has been added to the Undertow Suite, the Veritools' Assertion Analyzer.”

 

      

 

Supported Environments:

  • PSL/SystemVerilog assertion support using simulator evaluation

  • Verilog/VHDL/SystemVerilog assertion support using waveform evaluation with Assertion Analyzer

Functional Verification Coverage:

  • Analysis of hold and fail conditions

  • Display of assertions in the waveform window with the signals that caused the hold condition

  • Features that allow the user to do a ‘what if’ analysis of the assertions that fail so users can determine quickly why the assertion failed

Want more info? Download the following Data Sheets:

 

Undertow Suite 2004

PSL/SystemVerilog Assertions

Undertow 2004 for Analog Designers

Support for Denali Memory

Support for Calibre

Power Tool

 

Would you like to get an evaluation copy?:

 

Request an Evaluation License

 

For further questions, email us at info@MonarchTechGroup.com

 

 

Cool  Application (6)

 

 

Diagnostic/Prognostic IP Library

Improves MTBF by 5X!!!

 

Semiconductors don't live forever. Eventually they die, and often they die prematurely. PROGNOSTICS is the process of giving "advanced notification". The idea of incorporating a Prognostic Cell is to predict an end-of-life event before it occurs. This advance warning provides the means to mitigate the effects of the device or system

failure before it is catastrophic.

 

When used with event-driven maintenance, Prognostic Cell methodology will effectively increase the mean-time-between-failure (MTBF) five fold (see C&D Technologies, Inc. News Release: Electronic Prognostics added to DC/DC Converters).

 

Ridgetop Group, Inc. specializes in the design, layout, testing and characterization of reusable Sentinel Silicon™ diagnostic/prognostic cells for IC’s, including a Hot Carrier Prognostic Cell, a Metal Migration Prognostic Cell, a Time Dependent Dielectric Breakdown (TDDB) Prognostic Cell, an ESD Damage Cell and several Radiation Effect Prognostic Cells. These prognostic cells can be co-located with the host design on the IC substrate and package, quietly and unobtrusively monitoring. In effect, they are the “canary in the mine”, notifying the user of an impending failure event, and facilitating the corrective, evasive or mitigating action that is required.

 

 

Diagnostic/Prognostic IP Libraries

 Sentinel Silicon™ Application Guide

 ESD Cell 
 Hot Carrier Cell
 Metal Migration Cell
 Dielectric Breakdown Cell
 Radiation Effects Cell

 

 

For further questions, email us at info@MonarchTechGroup.com

Die Level Verification Monitor

 PDKChek

 

Radiation-Hardened Design Libraries

 InstaCell

 InstaCell IP Catalog

 

 

Built-in Self Test Libraries

 InstaBist Application Guide

 

 

 

 

 

The Monarch "eVC Shop"

 

 

CADENCE LETTER TO VERISITY CUSTOMERS

On February 18th. Cadence's CEO, Mike Fister, sent out a letter to Verisity users insuring that Cadence would continue supporting Verisity products. See the full text  Mike Fister Verisity Letter.pdf

 

The Monarch "eVC Shop" is an outlet for 3rd party verification IP components for Verisity's Specman Elite tool. These e language verification programs are plug-&-play solutions for testing and debugging Standard Protocols and interfaces. Here are 14 eVCs currently available through Monarch Technologies Group:

AND FOR THOSE OF YOU WHO'S BOSS WON'T LET THEM BUY VERISITY, HERE IS A NEW VERIFICATION IP IN VERILOG:

 

OCP 2.0 PSL Checker (Verilog)  Open Core Protocol - PSL Checker

 

For more information contact Bill Hoolhorst at BillH@MonarchTechGroup.com

 

 

What's New

 

 

 

News

 

Ridgetop Group Inc. receives $1,000,000 Contract from NAVAIR.  read more >>

(see related "Cool Application (6)" above).

 

Cadence's CEO, Mike Fister, sent out a letter to Verisity users insuring that Cadence would continue supporting Verisity products. read more >>

 

HDL Works releases HDL Companion 1.2   read more >>

Now available as a $1,295 Hierarchical Analysis upgrade to the popular free browser, Scriptum, released last month.

 

 

March/April - Advanced Seminars for Engineering Professionals

0ffered by the Silicon Valley Technical Institute

 

March 21, 2005

9:00am - 12:00pm - Design of sub-90nm CMOS Circuits and Design Methodologies
Ruchir Puri, Research Staff Member, IBM TJ Watson Research Center, NY
Sachin Sapatnaker, Professor, Electrical & Computer Engineering, University of Minnesota
Tanay Karnik, Principal Engineer, Intel Circuit Research Labs, Hillsboro, OR
Rajiv Joshi, Research Staff Member, IBM T J Watson Research Center, NY

 

March 21, 2005

1:00pm - 5:00pm   Modeling and Design of Chip-Package Interface
Luca Daniel, Massachusetts Institute of Technology, Cambridge, MA
Byron Krauter, IBM Microelectronics, Austin, TX
Lei He, UCLA EE Dept, Los Angeles, CA

 

March 22, 2005

7:00pm - 9:00pm  Expert Panel discussion (ISQED05) - Nanoelectronics: Breakthroughs and Barriers
Philip Wong - Stanford University and formerly IBM
Kazuo Yano - Hitachi - Central Research Lab - Research manager
Robert Doering - TI Senior Fellow - nanotechnology
Wilfried Haensch - IBM Yorktown
Shekhar Borkar - Intel Fellow - circuits
Franz Kreupl - Infineon - Corporate Research Labs
Andre DeHon - Caltech


April 12-13, 2005

9:00am - 4:00pm   Flash Memories and Embedded Flash - Application, Product and Technology
Dr. Prince, CEO of Memory International and an authority in Semiconductor Memory Technology



Please register on-line (http://www.svtii.com). Save money by registering prior to the advance registration deadline. Seating is limited so you are encouraged to register in advance. To obtain information about these and other seminars/workshops please visit http://www.svtii.com and check the "calendar of training programs".

 

 

Help Wanted - Engineering and Teaching

 

http://www.svtii.com/jobs.htm for Silicon Valley positions.

 

MONARCH TECHNOLOGIES GROUP PORTFOLIO

Data Sheets, White Papers & Down-loads

 

HDL Works has 2 products for HDL development. They both offer the novice and experienced HDL designers a flexible way to manage and develop their HDL projects.

Download EASE Data Sheet EASE Data Sheet

Download HDL Companion Data Sheet HDL Companion

Free HDL Text editor Scriptum

Web Site: www.hdlworks.com

 

 

 

Ridgetop Group provides semiconductor verification IP for silicon process and prognostic analysis.

Die Level Verification Monitor PDKChek

Diagnostic/Prognostic IP Library Application Guide Sentinel Silicon

VHDL-AMS/FD Harmonic Balance Simulator RINCON

Web Site: www.ridgetop-group.com

 

 

Veritools provides source code debugging and waveform viewing tools for Design, Verification, Testbench, and Assertion Analysis.

Undertow Debugger & Waveform Analyzer Undertow Suite 2004

Undertow for Analog Designers Undertow 2004 for Analog Designers

Undertow Assertion Analysis PSL/SystemVerilog Assertions

Web Site: http://www.veritools.com/

 

 

Ascend Design Automation can compile Verilog cores and test-benches to SystemC models.

 

Download Data Sheet Verilog to SystemC Data Sheet.

Download White Paper Verilog to SystemC White Paper.

Web Site: www.ascend-eda.com

 

 

 

 Alternative System Concepts:  Translators for the conversion of VHDL-to-Verilog, & Verilog-to-VHDL.

 

Download Verilog-to-VHDL Data Sheet http://www.ascinc.com/products/verilog2vhdl/node1.html

Download VHDL-to-Verilog Data Sheet http://www.ascinc.com/products/VHDL2verilog/node1.html

Web Site: www.ascinc.com

 

 

Runtime Design Automation provides the only tool designed for EDA that manages all your design bandwidth - staff, licenses, and CPUs, with a single toolset, from your web browser.

 

Download Flowtracer NC (network computing) Data Sheet: NC Data Sheet

Download Flowtracer EDA Data Sheet: EDA Data Sheet

Download PREEMPTION Application Note: PREEMPTION Application Note

View PREEMPTION Demo Videos: PREEMPTION Videos

Web Site: www.rtda.com

 

 

Yogitech  Verification Components (eVC) for use with Verisity's SpecMan software.

ATAPI 6 Device Download Data Sheet: ATAPI 6 Device eVC Leaflet

ATAPI 6 Host Download Data Sheet: ATAPI 6 Host eVC leaflet

OCP2.0 Download Data Sheet: OCP 2.0 eVC leaflet

CAN 2.0B Download Data Sheet: CAN 2.0B eVC leaflet

Y-CAN 2.0B Download Data Sheet: Y-CAN 2.0B

Web Site: www.yogitech.com

 

 

 

HDL Design House  Verification Components (eVC) for use with Verisity's SpecMan software.

SATA  Download Data Sheet:  HDH 2000  

HyperTransport  Download Data Sheet:  HDH 1000

Inter-IC (I2C)  Download Data Sheet: HDH 3000

RAPID IO  Download Data Sheet: HDH 5000

JTAG (IEEE 1149.1)  Download Data Sheet: HDH 6000

SAS  Download Data Sheet: HDH 7000

OCP 2.0 PSL Checker (Verilog)  Download Data Sheet: HVC 500

Web Site: www.hdl-dh.com

 

 

Paradigm Works  Verification Components (eVC) for use with Verisity's SpecMan software.

PCI EXPRESS  Download Data Sheet:  PCI Express  

ETHERNET  Download Data Sheet:  Ethernet

Web Site: www.paradigm-works.com

 

 

 

About Monarch Technologies Group
 

Monarch Technologies Group was formed in February of 2003 to provide a professional sales and marketing channel for suppliers of complex technology. Specifically, to provide an outsourced sales force for manufacturers of Electronic Design Automation (EDA) tools for the electronics engineering community. www.MonarchTechGroup.com

 

To Contact Us: Email at Info@MonarchTechGroup.com,  or Call (650) 366-0376

 

This newsletter is published as demand and content requires by Monarch Technologies Group, 235 Sylvan Way, Redwood City, CA 94062. +1-650-366-0376. Copyright 2005 by Monarch Technologies Group. Comments and submissions for publication should be sent to info@monarchtechgroup.com. All published articles are copyright by Monarch Technologies Group unless otherwise indicated.